Electronic Properties of High Mobility Solution-Processed Transparent Oxide
Transistors
Nikolaos A. Hastas
1*
, Hendrik Faber
1
, Yen-Hung Lin
1
, Alex D. Mottram
1
,
Thomas D. Anthopoulos
1
1
Department of Physics and Centre for Plastic Electronics, Blackett Laboratory, Imperial
College London, London SW7 2AZ, United Kingdom
* email:
Thin-film transistors (TFTs) based on metal oxide semiconductors represent an
emerging technology that promises to revolutionise large-area electronics due to the high
carrier mobility, optical transparency, mechanical flexibility and the potential for low-
temperature processing. The performance of TFTs depends strongly on the intrinsic
properties of the active layer material and though it is limited by them. In order to overcome
this limitation, low dimensional heterostructures based on transparent oxides grown have
been fabricated using sequentially staggered layers of intrinsically or extrinsically doped
materials. In these kind of structures, the majority carriers diffuse out from the extrinsically
doped semiconductor to the undoped layer or at the interface between them and form a two-
dimensional (2-DEG) electron gas. The confined electrons of the 2-DEG electron gas
minimizes the ionized impurity scattering of the carriers and thus increase the mobility of the
semiconductor which in many cases is higher than the mobility of the bulk semiconductor.
This 2-DEG confinement layer can be used as an active channel for implementation of high
mobility thin-film transistors
Usually, the electron gas confinement layer imposes high quality heterointerfaces
between the sequential grown layers and thus the experimentally observed devices have been
fabricated by molecular beam epitaxy or other epitaxial techniques at relatively high
temperatures and low pressure. A key challenge is to fabricate such electron confinement
layers using simpler, scalable and cost-effective fabrication processes, which are compatible
with low temperature substrate materials.
Here, low-dimensional polycrystalline structures consisting of alternating layers of
In
2
O
3
, Ga
2
O
3
and ZnO were grown by sequential spin casting or spray coating and thermally
annealed at temperatures in the range ≤ 250
℃
. The active channel material has been
deposited on different ultra-thin gate oxides which have been fabricated also by solution
processing in order to minimize the operating voltage and enhance the performance of the
transistors. High-k dielectrics of Al
2
O
3
, ZrO
2
, HfO
2
have been used as gate oxide showing
that the oxide/semiconductor interface is dominating on the performance of single layer
transistors.
Determination of deep and tail states distribution in the energy gap of the active
channel semiconductor has shown that the interfaces between sequential layers play a
significant role to the mobility enhancement and 2-DEG electron confinement between the
layers. Furthermore, the oxide/semiconductor interface is also critical for the trap density and
the mobility of free carriers inside the semiconductor. Further work on band structure
engineering could lead to the enhancement of localized electron confinement, increasing
further the electron charge density and the mobility of TFTs.
Capacitance (CV) measurements of metal-insulator-semiconductor (MIS) reveals the
spatial and energy distribution of traps which depends directly on the sequence of the
semiconductor layers deposited and the quality of the interfaces between the semiconductor
layers in case of multilayer structures.
O 4
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